| Proj No. | A2194-251 |
| Title | The Design of a Segmented Current Steering Digital-to Analog Converter (SCSDAC) with 4-bit unary and 6-bit binary. |
| Summary | The segmented CSDAC consists of 4-bit unary of a more significant bit weightage, a 6-bit binary of a lesser significant bit weightage together with the control logic. It uses weighted current mirrors that are diverted by the digital equivalent codes of an analog value through a current-to-voltage feedback amplifier to reproduce the analog signal. The use of W-2W network is used for the binary current weightage whereas the unary current mirrors are for the MSB. Though 55nm CMOS technology is used, the maximum supply is 1.8V using the higher VT device. The design will be an analog/ mixed-signal IC Design project that could work with frequency in excess of 100MHz. This is a very challenging project for a student who has good analog electronic knowledge and strong interest in analog/mixed-signal Integrated Circuit(IC) Design. Student should be in the electronic option with the IC Design specialization. |
| Supervisor | A/P Siek Liter (Loc:S2 > S2 B2C > S2 B2C 106, Ext: +65 67905441) |
| Co-Supervisor | - |
| RI Co-Supervisor | - |
| Lab | IC DESIGN I (Loc: S1-B2B-13) |
| Single/Group: | Single |
| Area: | Smart Electronics and IC design |
| ISP/RI/SMP/SCP?: |