| Proj No. | A2183-251 |
| Title | Design of an input and output Rail-to-Rail Analog Buffer |
| Summary | The design of an input ground compatible Op-Amp with driving capability that is able to source and sink current. It is use as a buffer providing analog ground at half Vdd for some applications or it can also be used as a signal buffer hence it should be able to handle output rail-to-rail swings. This design will be in the 55nm CMOS and/or BCB-lite technology, and should be able to work down from a maximum of 1.8V to 0.9V power supply or lower with 60 degrees phase margin, GBW of 50MHz, open-loop gain of about 80dB, with an input-referred noise of about 500nV/sq.rt.Hz at 1kHz. The driving capability of the amplifier is for 60pF, and resistive load with current upto 10mA. Layout should be done after satisfying all corner simulations, and later with post-layout simulation. This is suitable for a student with strong inclination towards analog IC Design. |
| Supervisor | A/P Siek Liter (Loc:S2 > S2 B2C > S2 B2C 106, Ext: +65 67905441) |
| Co-Supervisor | - |
| RI Co-Supervisor | - |
| Lab | IC DESIGN I (Loc: S1-B2B-13) |
| Single/Group: | Single |
| Area: | Smart Electronics and IC design |
| ISP/RI/SMP/SCP?: |