| Proj No. | A2185-251 |
| Title | DESIGN OF A LOW POWER AND LOW VOLTAGE PLL |
| Summary | This project aims to design a PLL with an input reference frequency of 50MHz and an output frequency of 200MHz. The PLL consists of a Phase-Frequency Detector (PFD), charge pump, Low Pass Filter (LPF), Voltage control Oscillator (VCO) and a divided-by-4 frequency divider in the feedback path. The PLL should feature good jitter performance with low power consumption. Cadence tools, Virtuoso will be used for circuit implementation and verification. Layout physical implementation will be completed with post layout simulations to be included if time permits. The design will be in the 55nm BCD-lite technology and should be able to work down from a maximum of 1.8V to 1.2V power supply or lower. This project is most suitable for student in the electronic option with specialization in IC Design with a good knowledge in analog circuits. |
| Supervisor | A/P Siek Liter (Loc:S2 > S2 B2C > S2 B2C 106, Ext: +65 67905441) |
| Co-Supervisor | - |
| RI Co-Supervisor | - |
| Lab | IC DESIGN I (Loc: S1-B2B-13) |
| Single/Group: | Single |
| Area: | Smart Electronics and IC design |
| ISP/RI/SMP/SCP?: |