| Proj No. | A2191-251 |
| Title | Design of a Low Voltage High Speed Comparator with Tunable Hysteresis Window |
| Summary | Comparators are found in many applications, for use to compare different voltage level against a reference. However, if the compared voltage level comes close to the reference, the speed becomes slow, and far worst if noise is included. There exists metastabilty and indecision hence a built-in hysteresis window could be used to overcome this problem. In this project, the design should include a tunable hysteresis window, such that it can be used for a wider range of applications. The biasing is supplied through a constant Gm wide-swing cascode circuit such as to achieve a good PSRR for the entire design. The design will be implemented in 55nm CMOS/BCD Lite technology with a supply of 1.8 V or lower, speed response in nano-second domain or lower with the simulations to clear all corners and circuit layout should be included for completeness only if time permits with post layout simulations. This project is suitable for student with an inclination towards analog IC Design. |
| Supervisor | A/P Siek Liter (Loc:S2 > S2 B2C > S2 B2C 106, Ext: +65 67905441) |
| Co-Supervisor | - |
| RI Co-Supervisor | - |
| Lab | IC DESIGN I (Loc: S1-B2B-13) |
| Single/Group: | Single |
| Area: | Smart Electronics and IC design |
| ISP/RI/SMP/SCP?: |