| Proj No. | A2040-251 |
| Title | A 40nm CMOS Current Reference for Internet-of-Things Applications |
| Summary | A low-power current reference is important for IoT applications in context of the design challenge for low-quiescent design to cope with variations in process, supply voltage and temperature (PVT). The objective of this project is to explore the design of an alternative circuit architecture for a 40 nm CMOS current reference dedicated to low level biasing generation for IoT circuits and systems applications. The Cadence EDA tools will be used for simulation and verification. |
| Supervisor | A/P Chan Pak Kwong (Loc:S1 > S1 B1B > S1 B1B 45, Ext: +65 67904513) |
| Co-Supervisor | - |
| RI Co-Supervisor | - |
| Lab | IC DESIGN I (Loc: S1-B2B-13) |
| Single/Group: | Single |
| Area: | Smart Electronics and IC design |
| ISP/RI/SMP/SCP?: |