| Proj No. | A2092-251 |
| Title | An Asynchronous-Logic Pipeline Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations on FPGA |
| Summary | With the increasing deployment of cryptographic accelerators in edge computing, AI applications, and IoT devices, hardware security threats, particularly side-channel attacks (SCAs), have become a significant concern. SCAs exploit physical leakage information from cryptographic hardware, such as power consumption and electromagnetic (EM) emissions, to extract secret keys. Traditional synchronous-logic AES accelerators, while effective in securing data, remain vulnerable to these attacks. Asynchronous-logic (async-logic) circuits have been explored as a potential countermeasure due to their inherent power and timing variations, making SCAs more difficult. However, most existing async-logic AES implementations focus only on hiding techniques, without fully integrating masking countermeasures. Masking introduces randomness in intermediate computations, making it difficult for attackers to correlate leaked signals with encryption keys. This project proposes an FPGA-based implementation of an async-logic pipeline AES accelerator with integrated masking and hiding countermeasures. The security of the design will be evaluated through practical SCA experiments on an FPGA platform, using CPA (Correlation Power Analysis) and CEMA (Correlation Electromagnetic Analysis) techniques. |
| Supervisor | A/P Gwee Bah Hwee (Loc:S1 > S1 B1B > S1 B1B 42, Ext: +65 67906861) |
| Co-Supervisor | - |
| RI Co-Supervisor | - |
| Lab | IC DESIGN II (Loc: S1-B2B-10) |
| Single/Group: | Single |
| Area: | Smart Electronics and IC design |
| ISP/RI/SMP/SCP?: |