| Proj No. | B2170-251 |
| Title | Deep learning Approaches for Wirebond Defect Detection |
| Summary | Integrated circuits are the foundation of the digital era, enabling advances across all fields and becoming indispensable to modern society. Semiconductor manufacturing involves three key stages: wafer fabrication, assembly/packaging, and testing. This project focuses on ensuring reliability at the packaging stage through the development of an automated inspection pipeline for wire bond quality in integrated circuits. The objective is to automatically identify common defects and verify wire continuity using machine learning and deep learning techniques. A major challenge lies in achieving high-throughput, real-time inspection from X-ray images, which are often highly variable due to differences in imaging conditions and package geometries. Moreover, X-ray images in industrial settings are typically low contrast and noisy, as systems prioritize fast acquisition over image quality. To address these issues, the project investigates advanced contrast-enhancement methods, robust segmentation approaches, and modern architectures such as U-Net. In addition, the use of FPGA acceleration enables streaming pipelines for preprocessing, contrast enhancement, and large-scale data augmentation. This project explores, by combining deep learning algorithms with FPGA-based acceleration, an inspection solution for real-time and high-throughput inspection for wirebond defect detection. |
| Supervisor | A/P Poenar Daniel Puiu (Loc:S2 > S2 B2A > S2 B2A 27, Ext: +65 67904237) |
| Co-Supervisor | - |
| RI Co-Supervisor | - |
| Lab | Machine Learning and Data Analytics Lab (Loc: S2.1-B4-01) |
| Single/Group: | Single |
| Area: | Intelligent Systems and Control Engineering |
| ISP/RI/SMP/SCP?: | ISP: Dr. Seck Hon Luen Senior Scientist II Singapore Institute of Manufacturing (SIMTech) hlseck@SIMTech.a-star.edu.sg |