| Proj No. | A2121-251 |
| Title | Design Low voltage SRAM for IoT Applications |
| Summary | Memory is a critical building block in numerous applications. The density of memory has been dramatically increased following Moore's law. However, design of memory is evermore challenging due to various requirements such as small device sizes, low voltage operation, and low power consumption. Small device sizes are indispensable in memory design to improve the area efficiency even if they show larger process fluctuations. The process fluctuations are becoming even worse in more advanced technologies. The process fluctuations deteriorate memory cell stability and write/read operations more likely generating failures. Low voltage operation and low power consumption are also highly required to increase power/energy efficiency and battery lifetime. One example of low voltage and low power memory is subthreshold SRAMs for minimum energy consumption. They have various promising applications such as implantable biomedical devices, portable electronics, wireless sensor nodes, and so forth. In this project, students will design an ultra-low voltage SRAM for high energy efficiency. |
| Supervisor | A/P Kim Tae Hyoung (Loc:S2 > S2 B2B > S2 B2B 42, Ext: +65 67904001) |
| Co-Supervisor | - |
| RI Co-Supervisor | - |
| Lab | VIRTUS, IC Design Centre of Excellence (Loc: S3.2-B2 Tel 6592 1844) |
| Single/Group: | Single |
| Area: | Smart Electronics and IC design |
| ISP/RI/SMP/SCP?: |