| Proj No. | A2088-251 |
| Title | Graph Machine Learning for Hardware Security of Digital Integrated Circuits (IC) |
| Summary | Hardware security of digital Integrated Circuits (IC) would frequently require the extraction and analysis of its netlist, which is a detailed description of its circuitry. Given the large scale of today’s IC with billions of logic gates, this analysis is extremely difficult if not impossible. Recently, researchers have explored the method of converting the netlist of a digital IC to its corresponding circuit graph with logic gates as nodes and their interconnections as edges, and subsequently applying various Graph Machine Learning (GML) methods to analyse it. In this project, we will explore using GML for detecting circuit of interest from a large circuit netlist. Our focus will be on circuit detection on ASIC (Application-Specific IC) netlists. Throughout this project, the student will learn the latest developments in GML and machine learning techniques in general. The student will also have the opportunity to work on state-of-the-art machine learning models using advanced GPU workstations. |
| Supervisor | A/P Gwee Bah Hwee (Loc:S1 > S1 B1B > S1 B1B 42, Ext: +65 67906861) |
| Co-Supervisor | - |
| RI Co-Supervisor | - |
| Lab | IC DESIGN I (Loc: S1-B2B-13) |
| Single/Group: | Single |
| Area: | Intelligent Systems and Control Engineering |
| ISP/RI/SMP/SCP?: |