| Proj No. | A2267-251 |
| Title | Design of Reconfigurable Transistors Using 2D Ferroelectric Materials for Logic Applications |
| Summary | With the increasing demand for energy-efficient and highly adaptable electronic devices, reconfigurable logic transistors have emerged as a promising alternative to conventional complementary metal-oxide-semiconductor (CMOS) technology. Unlike traditional transistors with fixed functionalities, reconfigurable transistors can dynamically switch between different logic states, enabling more versatile and power-efficient computing architectures. This feature is particularly crucial for next-generation computing paradigms, such as in-memory computing and neuromorphic systems. 2D ferroelectric materials, owing to their ultra-thin nature, non-volatile polarization states, and excellent electrostatic control, have garnered significant attention as potential candidates for reconfigurable transistor applications. These materials exhibit spontaneous polarization that can be reversed by an external electric field, allowing for non-volatile memory effects and tunable electronic properties. Such characteristics make 2D ferroelectric materials highly suitable for energy-efficient logic operations, reconfigurable circuits, and even brain-inspired computing systems. Despite their promising features, several challenges hinder the practical implementation of 2D ferroelectric transistors. One major limitation is the need for reliable ferroelectric switching with minimal fatigue and retention loss. Additionally, achieving high on/off ratios and low subthreshold swings while maintaining stable multi-state switching remains an ongoing research challenge. There is also a need for scalable fabrication techniques that can integrate 2D ferroelectric materials into existing semiconductor technologies without compromising device performance. This proposed project aims to explore the design, fabrication, and electrical characterization of reconfigurable transistors based on 2D ferroelectric materials. The research will focus on optimizing material properties, device structures, and switching mechanisms to enhance performance for logic applications. |
| Supervisor | Prof Tay Beng Kang (Loc:S1 > S1 B1A > S1 B1A 29, Ext: +65 67904533) |
| Co-Supervisor | - |
| RI Co-Supervisor | - |
| Lab | Nanoelectronics Lab. I (Loc: S1-B3a-01) |
| Single/Group: | Single |
| Area: | Microelectronics and Biomedical Electronics |
| ISP/RI/SMP/SCP?: |