| Proj No. | A2045-251 |
| Title | Impact of Round Modifications on Cryptanalysis and Side-Channel Attacks in AES and ASCON |
| Summary | This project explores the effects of modifying the number of rounds and operations in each round (such as altering the S-boxes structure or modifying the key schedule) in the advanced encryption standard (AES), Authenticated Encryption with Associated Data in Constant Time (ASCON) and other cryptographic algorithms on their resistance to cryptanalysis and side-channel attacks (SCAs). AES, a widely-used block cipher, and Ascon, a lightweight cipher for resource-constrained devices, rely on rounds for security. Altering the round count could impact their vulnerability to attacks such as differential, linear cryptanalysis, and SCAs like power/EM analysis. In general, instead of repeating rounds, modifying operations in each round would have an impact on cryptanalysis and side channel attacks. The objectives of this project are: 1 Review of AES and Ascon: Study their round structures and existing research on round modifications. 2. Algorithm Modification: Change the number of rounds, and alter operations in each rounds in AES and Ascon implementations. 3. Cryptanalysis: Evaluate the modified algorithms using differential cryptanalysis, and brute-force attacks. 4. Side-Channel Attack Simulation: Perform power analysis and timing attacks to assess vulnerability- and try to prevent using different operations in rounds. 5. Performance Analysis: Compare the trade-offs between security and efficiency. This project will provide insights into how changing rounds operations affects the cryptographic strength and vulnerability to SCAs of AES and ASCON, offering guidance for optimizing security in cryptographic systems, especially in lightweight and IoT contexts. Students who wish to work on this project are encouraged to contact the supervisor for more information before making the selection. |
| Supervisor | Prof Chang Chip Hong (Loc:S2 > S2 B2C > S2 B2C 97, Ext: +65 67905873) |
| Co-Supervisor | - |
| RI Co-Supervisor | - |
| Lab | VIRTUS, IC Design Centre of Excellence (Loc: S3.2-B2 Tel 6592 1844) |
| Single/Group: | Single |
| Area: | Smart Electronics and IC design |
| ISP/RI/SMP/SCP?: |