| Proj No. | A2043-251 |
| Title | Hardware Implementation of Spiking Neural Network-based Physical Unclonable Function |
| Summary | Physical Unclonable Functions (PUFs) play a crucial role in hardware security. PUFs rely on semiconductor manufacturing manufacturing process variations to derive device unique fingerprint from each identically designed chip for secret key generation. Emerging threats and advanced attack techniques necessitate more robust PUF circuit architectures. This project aims to integrate Spiking Neural Networks (SNNs) with PUFs (SNN+PUF) to harvest not only static entropy from the SNN hardware but also the dynamic entropy of SNN data to enhance the security of device-specific key generation. A temporal neuromorphic PUFs that exploits spectro-temporal information inherent in sensor data (e.g., event cameras, biomedical sensors) to reconfigure the challenge-response (CR) space will be studied and evaluated to determine its resistance against machine-learning based modeling attacks. Existing PUF implementations focus mainly on static challenge-response pairs without considering the temporal dynamics of neuromorphic sensors. This project aims to develop a new hardware-intrinsic SNN+PUF implementation on a Field Programmable Gate Array (FPGA) platform to capitalize the efficiency and low-power characteristics of neuromorphic computing. The project consists of three key phases: 1. Algorithm Development and Optimization: Explore and optimize SNN architectures to generate robust and unpredictable PUF responses that are resistant to machine learning attacks. 2. Hardware Implementation: Build an FPGA-based hardware platform to integrate and evaluate the SNN+PUF system, using neuromorphic data from dynamic vision sensors (DVS) and biomedical sensors. 3. Performance Evaluation and Security Analysis: Conduct quality tests using diverse datasets, analyze security robustness against potential attacks for a proof-of-concept prototype. This project involves secure, low-power neuromorphic hardware design. Ultimately, it contributes to brain-inspired neuromorphic security architectures to protect smart applications in resource-constrained environments. Students who wish to take up this project are encouraged to contact the supervisor before making the selection. |
| Supervisor | Prof Chang Chip Hong (Loc:S2 > S2 B2C > S2 B2C 97, Ext: +65 67905873) |
| Co-Supervisor | - |
| RI Co-Supervisor | - |
| Lab | VIRTUS, IC Design Centre of Excellence (Loc: S3.2-B2 Tel 6592 1844) |
| Single/Group: | Single |
| Area: | Smart Electronics and IC design |
| ISP/RI/SMP/SCP?: |