| Proj No. | A2048-251 |
| Title | Extreme-Density, Ultra-Efficient Power Management Unit Design for Next-Generation AI Hyperscale Data Centers |
| Summary | The artificial intelligence (AI) revolution is driving the global expansion of hyperscale data centers, leading to a surge in the demand for energy, land, water, and other resources. These sprawling facilities host vast, high-density computing resources and storage infrastructure, densely packed into racks of servers. As the complexity of AI training and inference continues to grow, next-generation AI hyperscalers are confronted with the challenge of addressing the rapidly rising power density demand of these server racks. Specifically, power management units delivering energy to these racks are expected to double their density by the end of the decade to an exceptional 2 kW per cubic inch, while simultaneously achieving power efficiency as close to 100% as possible. Overcoming these challenges is critical to minimizing the resources needed to power, accommodate, and cool these hyperscale facilities. Nonetheless, these challenges remain unresolved due to the limitations of today’s power management units. At this juncture, state-of-the-art designs achieve approximately 97% efficiency at a density of less than 1 kW per cubic inch. While impressive, these specifications fall short of meeting the unprecedented requirements. Put simply, there is a real and unresolved need for extremely high-density, ultra-efficient power management units for next-generation AI hyperscalers. This project aims to design a revolutionary power management unit that pushes the boundaries of both density and efficiency. The target specifications aim for an unprecedented power density exceeding 1.8 kW per cubic inch, coupled with an efficiency of 98% or greater-effectively doubling density and improving efficiency by 1%. To achieve these goals, this project will employ a comprehensive, multidisciplinary approach encompassing advanced circuit design, innovative transformer technology, and cutting-edge printed-circuit-board engineering. |
| Supervisor | Prof Chang, Joseph Sylvester (Loc:S1 > S1 B1B > S1 B1B 60, Ext: +65 67904424) |
| Co-Supervisor | - |
| RI Co-Supervisor | - |
| Lab | INTEGRATED SYSTEMS RESEARCH (Loc: S1-B2A-04) |
| Single/Group: | Single |
| Area: | Smart Electronics and IC design |
| ISP/RI/SMP/SCP?: |