| Proj No. | A2285-251 |
| Title | Efficient Hardware-Software Co-design for Large Language Models |
| Summary | Large language models (LLMs) are shaping today’s world as personal assistants (e.g. ChatGPT). However, they require a large amount of hardware resources to be deployed. In particular, it is challenging to run them on edge devices with limited memory and processing units. This project aims to design efficient and lightweight hardware specifically for LLMs. LLMs are bottlenecked by large matrix multiplications and time-consuming non-linear operations such as SoftMax. To overcome the performance bottleneck, specialized hardware implementations on reconfigurable devices can be explored for acceleration. Field Programmable Gate Arrays (FPGAs) are off-the-shelf silicon devices that provide software-like adaptability and custom hardware-like performance to accelerate digital signal processing algorithms. With highly flexible fine-grained parallelism, FPGA-based accelerators can provide high throughput and low latency data processing. |
| Supervisor | Prof Chang Chip Hong (Loc:S2 > S2 B2C > S2 B2C 97, Ext: +65 67905873) |
| Co-Supervisor | - |
| RI Co-Supervisor | - |
| Lab | |
| Single/Group: | Single |
| Area: | Digital Media Processing and Computer Engineering |
| ISP/RI/SMP/SCP?: |